STM32F401 datasheet(79/135 Pages) STMICROELECTRONICS

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STM32F401xD STM32F401xE

Electrical characteristics

114

series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF

can be used as a rough estimate of the combined pin and board capacitance) when sizing

CL1 and CL2.

Note:

For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 24. Typical application with an 8 MHz crystal

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 38. In

the application, the resonator and the load capacitors have to be placed as close as

possible to the oscillator pins in order to minimize output distortion and startup stabilization

time. Refer to the crystal resonator manufacturer for more details on the resonator

characteristics (frequency, package, accuracy).

Note:

For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz) (1)

1. Guaranteed by design, not tested in production.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Feedback resistor

18.4

IDD

LSE current consumption

µA

Gm_crit_max Maximum critical crystal gm

Startup

0.56

µA/V

tSU(LSE)(2)

2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is guaranteed by characterization and not tested in

production. It is measured for a standard crystal resonator and it can vary significantly with the crystal

manufacturer.

startup time

VDD is stabilized

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