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ST-PLC-AFE 데이터시트(PDF) 12 Page - STMicroelectronics |
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ST-PLC-AFE 데이터시트(HTML) 12 Page - STMicroelectronics |
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12 / 58 page ![]() General description ST-PLC-AFE 12/58 DocID028727 Rev 1 Figure 6. Connection to the power line in single-ended mode This mode requests an external clock generator from the MCU. See Section 6 for the constraints related to this conduction mode. 2.2.2 External driving mode, differential-ended power amplifier mode Figure 7 shows the differential coupling with the power line. The input signal is driven with an external DAC. When in external driving mode, the ST-PLC-AFE accepts being driven by analog through the TX_INP input pin. In this case, TX_INN has to be connected to the pin MID_AVDD (pin 22). External drive mode is selected by setting the DAC_EN bit in the Enable register to 0. Figure 7. External driving mode using an external DAC |
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