TUSB4041IPAP datasheet(18/44 Pages) TI1

18 / 44 page

TUSB4041I

SLLSEK3B – JULY 2015 – REVISED DECEMBER 2015

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Table 9. Device Configuration Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Ganged

This bit is loaded at the deassertion of reset with the value of the

GANGED/SMBA2/HS_UP pin.

0 = Each port is individually power switched and enabled by the

PWRCTL[4:1]/BATEN[4:1] pins.

ganged

1 = The power switch control for all ports is ganged and enabled by the

PWRCTL[4:1]/BATEN1 pin.

When the TUSB4041I device is in I2C mode, the TUSB4041I device loads this bit

from the contents of the EEPROM.

When the TUSB4041I device is in SMBUS mode, the value may be overwritten by

an SMBus host.

Full power management

This bit is loaded at the deassertion of reset with the value of the

FULLPWRMGMTz/SMBA1 pin.

0 = Port power switching status reporting is enabled

fullPwrMgmtz

1 = Port power switching status reporting is disabled

When the TUSB4041I device is in I2C mode, the TUSB4041I device loads this bit

from the contents of the EEPROM.

When the TUSB4041I device is in SMBUS mode, the value may be overwritten by

an SMBus host.

Reserved

RSVD

This field is reserved and should not be altered from the default.

Reserved

RSVD

This field is reserved and returns 0 when read.

8.5.8 Battery Charging Support Register

Offset = 6h

Figure 9. Battery Charging Support Register

RSVD

batEn[3:0]

R-0

RW-X

Table 10. Battery Charging Support Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7:4

RSVD

Read only, returns 0 when read.

Battery Charger Support. The bits in this field indicate whether the downstream port

implements the charging port features.

0 = The port is not enabled for battery charging support features

1 = The port is enabled for battery charging support features

3:0

batEn[3:0]

Each bit corresponds directly to a downstream port, that is batEn0 corresponds to

downstream port 1, and batEN1 corresponds to downstream port 2.

The default value for these bits are loaded at the deassertion of reset with the value

of PWRCTL/BATEN[3:0].

When in I2C/SMBus mode the bits in this field may be overwritten by EEPROM

contents or by an SMBus host.

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