XIO2001IPNP datasheet(3/141 Pages) TI1

3 / 141 page

XIO2001

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SCPS212I – MAY 2009 – REVISED JANUARY 2016

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Table of Contents

Features .................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 3

Pin Configuration and Functions ......................... 5

5.1

Pin Assignments ....................................................... 5

5.2

Pin Descriptions ........................................................ 8

Specifications....................................................... 15

6.1

Absolute Maximum Ratings .................................... 15

6.2

Handling Ratings..................................................... 15

6.3

Recommended Operating Conditions ..................... 15

6.4

Thermal Information ............................................... 16

6.5

Nominal Power Consumption ................................. 17

6.6

PCI Express Differential Transmitter Output

Ranges..................................................................... 17

6.7

PCI Express Differential Receiver Input Ranges .... 18

6.8

PCI Express Differential Reference Clock Input

Ranges .................................................................... 19

6.9

PCI Bus Electrical Characteristics ......................... 20

6.10

3.3-V I/O Electrical Characteristics ...................... 20

6.11

PCI Bus Timing Requirements ............................. 21

6.12

Power-Up/-Down Sequencing............................... 21

Parameter Measurement Information ................ 24

Detailed Description ............................................ 26

8.1

Overview ................................................................. 26

8.2

Functional Block Diagram ....................................... 26

8.3

Feature Description................................................. 26

8.4

8.5

PCI Express Extended Configuration Space .......... 91

8.6

Memory-Mapped TI Proprietary Register Space .. 102

Application, Implementation, and Layout ....... 114

9.1

Application Information.......................................... 114

9.2

Typical Application ................................................ 114

9.3

Layout ................................................................... 124

9.4

Power Supply Recommendations ......................... 127

Device and Documentation Support ............... 130

10.1

Documents Conventions ..................................... 130

10.2

Documentation Support ...................................... 131

10.3

Trademarks ......................................................... 131

10.4

Electrostatic Discharge Caution .......................... 131

10.5

Glossary .............................................................. 131

Mechanical, Packaging, and Orderable

Information ......................................................... 131

4 Revision History

REVISION

DATE

REVISION

NUMBER

REVISION COMMENTS

5/2009

–

Initial release

5/2009

Corrected typos

9/2009

10/2009

Added PNP Package and ESD Ratings

Removed terminal assignment tables for all packages

1/2010

Corrected PNP pinout, replaced Ordering Information with Package Option Addendum

11/2011

Corrected Vi PCI Express REFCLK(differential) parameters

Corrected VRX-DIFFp-p parameters

Removed label N13 on the signal VDD_15 for the ZAJ package

5/2012

Added missing PNP pin numbers to the Table 2-1 and to the Table 2-2

5/2012

Changed external parts for CLKRUN_EN to include pulldown resostor

Deleted Note from CLKRUIN_EN terminal's description

Changed external Parts for EXT_ARB_EN to include pulldown resistor

Deleted Note from EXT_ARB_EN terminal's description

8/2014

Added Pin Configuration and Functions section, Handling Rating table, Feature Description section,

Device Functional Modes, Application and Implementation section, Power Supply Recommendations

section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and

Orderable Information section

Updated Power-Up Sequence section

Identified VDD_15_PLL pins

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