전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

STM32F446VC 데이터시트(PDF) 125 Page - STMicroelectronics

부품명 STM32F446VC
상세설명  8- to 14-bit parallel camera interface up to 54 Mbytes
PDF  201 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F446VC 데이터시트(HTML) 125 Page - STMicroelectronics

Back Button STM32F446VC Datasheet HTML 121Page - STMicroelectronics STM32F446VC Datasheet HTML 122Page - STMicroelectronics STM32F446VC Datasheet HTML 123Page - STMicroelectronics STM32F446VC Datasheet HTML 124Page - STMicroelectronics STM32F446VC Datasheet HTML 125Page - STMicroelectronics STM32F446VC Datasheet HTML 126Page - STMicroelectronics STM32F446VC Datasheet HTML 127Page - STMicroelectronics STM32F446VC Datasheet HTML 128Page - STMicroelectronics STM32F446VC Datasheet HTML 129Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 125 / 201 page
background image
DocID027107 Rev 5
125/201
STM32F446xC/E
Electrical characteristics
174
open-drain. When configured as open-drain, the PMOS connected between the I/O pin and
VDD is disabled, but is still present.
The I2C characteristics are described in Table 61. Refer also to Section 6.3.17: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 61. I2C characteristics
Symbol
Parameter
Standard mode
I2C(1)(2)
1. Guaranteed based on test during characterization.
Fast mode I2C(1)(2)
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode
clock.
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
µs
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
ns
th(SDA)
SDA data hold time
-
3450(3)
3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
-900(4)
4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
tv(SDA, ACK) Data, ACK valid time
-
3.45
-
0.9
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
Start condition hold time
4.0
-
0.6
-
µs
tsu(STA)
Repeated Start condition
setup time
4.7
-
0.6
-
tsu(STO)
Stop condition setup time
4.0
-
0.6
-
μs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
μs
tSP
Pulse width of the spikes
that are suppressed by the
analog filter for standard and
fast mode
-
-
0.05
0.09(5)
5. The minimum width of the spikes filtered by the analog filter is above tSP(max).
μs
Cb
Capacitive load for each bus
line
-
400
-
400
pF



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com