STM32F446VC datasheet(130/201 Pages) STMICROELECTRONICS

130 / 201 page

Electrical characteristics

STM32F446xC/E

130/201

DocID027107 Rev 5

Figure 36. SPI timing diagram - slave mode and CPHA = 0

tw(SCKH)

SCK high and low time

Master mode, SPI presc = 2

TPCLK - 1.5

TPCLK TPCLK + 1.5

tw(SCKL)

tsu(NSS)

NSS setup time

Slave mode, SPI presc = 2

4TPCLK

th(NSS)

NSS hold time

Slave mode, SPI presc = 2

2TPCLK

tsu(MI)

Data input setup time

Master mode

tsu(SI)

Slave mode

th(MI)

Data input hold time

Master mode

th(SI)

Slave mode

ta(SO)

Data output access time Slave mode

tdis(SO)

Data output disable time Slave mode

tv(SO)

Data output valid/hold

time

Slave mode (after enable edge),

2.7V ≤ VDD ≤ 3.6V

-7.5

Slave mode (after enable edge),

1.7 V ≤ VDD ≤ 3.6 V

7.5

10.5

th(SO)

Data output valid/hold

time

Slave mode (after enable edge)

tv(MO)

Data output valid time

Master mode (after enable edge)

1.5

th(MO)

Data output hold time

Master mode (after enable edge)

1. Guaranteed based on test during characterization.

2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or

high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

having tsu(MI) = 0 while Duty(SCK) = 50%.

Table 63. SPI dynamic characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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