STM32F446VC datasheet(142/201 Pages) STMICROELECTRONICS

142 / 201 page

Electrical characteristics

STM32F446xC/E

142/201

DocID027107 Rev 5

Equation 1: RAIN max formula

The formula above (Equation 1) is used to determine the maximum external impedance

allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of

sampling periods defined in the ADC_SMPR1 register.

fS(2)

Sampling rate

(fADC = 30 MHz, and

tS = 3 ADC cycles)

12-bit resolution

Single ADC

Msps

12-bit resolution

Interleave Dual ADC

mode

3.75

Msps

12-bit resolution

Interleave Triple ADC

mode

Msps

IVREF+(2)

ADC VREF DC current

consumption in conversion

mode

300

500

µA

IVDDA(2)

ADC VDDA DC current

consumption in conversion

mode

1.6

1.8

1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2:

Internal reset OFF).

2. Guaranteed based on test during characterization.

3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.

4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.

5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 74.

Table 74. ADC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 75. ADC static accuracy at fADC = 18 MHz(1)

1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.

Symbol

Parameter

Test conditions

Typ

Max(2)

2. Guaranteed based on test during characterization.

Unit

Total unadjusted error

fADC =18 MHz

VDDA = 1.7 to 3.6 V

VREF = 1.7 to 3.6 V

VDDA −VREF < 1.2 V

±3

±4

LSB

Offset error

±2

±3

Gain error

±1

±3

Differential linearity error

±1

±2

Integral linearity error

±2

±3

RAIN

k0.5

–

()

fADC CADC

()

----------------------------------------------------------------

RADC

–

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