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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VS6955CA 데이터시트(PDF) 21 Page - STMicroelectronics |
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VS6955CA 데이터시트(HTML) 21 Page - STMicroelectronics |
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21 / 90 page  DocID028071 Rev 2 21/90 VS6955CA Functional description 21 3.6 Control and video interface formats Image data is transferred from the VS6955CA using a high speed subLVDS serial link.The serial control data is transferred to and from the VS6955CA using a CCI bus. 3.6.1 CCP/CSI-2 serial data link Data signals (DATA+ and DATA-) and clock signals (CLK+ and CLK-) are transferred from VS6955CA using two pairs of balanced 100 Ω impedance transmission lines. The transmission line pairs and custom transmitters/receivers realize a very low voltage differential (subLVDS) signalling scheme that can transfer information in a potentially noisy environment. For the CCP link or CSI-2 single lane interface, the VS6955CA supports the transmission of raw Bayer data at 5.0 Mpixel resolution up to 23 fps in RAW8 or 10-8 bit format. 3.6.2 CCI serial control bus The internal registers in VS6955CA can be configured by a master device via a CCI bus (SDA, SCL). VS6955CA sends and receives commands over this bus at up to 400 Kbits/s. |
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