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Data Sheet

AD9531

PLL3 Spurious Performance

Entries in Table 31 indicate the worst spur measured between dc and 600 MHz on OUT3_1P for the given conditions.

Table 31.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SPURIOUS PERFORMANCE

ROM Profile 4

PLL1: fR = 122.88 MHz, fLOOP = 300 kHz; PLL2: fR = 50 MHz

OUT2_0 to OUT2_4

−61

dBc

OUT2_5 to OUT2_7

−69

dBc

OUT2_8 to OUT2_11

−78

dBc

ROM Profile 5

PLL1: fR = 10 MHz, fVCXO = 122.88 MHz, fLOOP = 100 Hz; PLL2:

fR = 50 MHz; PLL3: fR = 10 MHz, CLOAD = 10 pF on OUT3_1P

OUT2_0

−76

dBc

OUT2_1

−65

dBc

OUT2_2 to OUT2_3

−69

dBc

OUT2_4 to OUT2_11

−79

dBc

PLL3 Jitter Generation

Unless otherwise specified the following test conditions apply: PLL1 configured with OUT1_0 to OUT1_9 operating at 122.88 MHz in HSTL

mode; PLL2 configured with fREF = 50 MHz, fVCO = 2.5 GHz, and OUT2_0 to OUT2_11 operating at 125 MHz in HSTL mode; PLL3

configured for single loop operation with OUT3_0 disabled. Measurements are valid with the PLL2 input reference locked to an integer

multiple of the PLL3 input reference frequency to within 4.8 ppm.

Table 32.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

JITTER GENERATION

fR = 25 MHz; fOUT = 100 MHz

OUT1_8x and OUT1_9x Disabled

1.78

ps rms

OUT1_8x and OUT1_9x Active

3.17

ps rms

fR = 10 MHz; fOUT = 125 MHz

PLL1 and PLL2 Powered Down

2.69

ps rms

OUT1_8x and OUT1_9x Disabled

2.95

ps rms

OUT1_8x and OUT1_9x Active

5.20

ps rms

PLL3 Start-Up Time

The PPL3 start-up time is the time from the application of power (90% of nominal) to the first output clock edge (PLL3 is locked and the

outputs are synchronized).

Table 33.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

START-UP TIME

fR = 10 MHz, fOUT = 25 MHz, fPFD = 10 MHz

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