3

LOW-NOISE DEVICE AND PACKAGE SOLUTIONS

Separate on-chip power and ground buses are provided for internal cells and output drivers which further isolate internal design

circuitry from switching noise.

In addition, Aeroflex offers advanced low-noise package technology with multi-layer, co-fired ceramic construction featuring built-

in isolated power and ground planes (Table 2). These planes provide lower overall resistance/inductance through power and ground

paths which minimize voltage drops during periods of heavy switching. These isolated planes also help sustain supply voltage dur-

ing dose rate events, thus preventing rail span collapse.

Flatpacks are available with up to 352 leads. PGAs are available with up to 299 pins and LGAs/CCGAs up to 624 pins. Aeroflex's

flatpacks feature a non-conductive tie bar that helps maintain lead integrity through test and handling operations.

In addition to the packages listed in Table 2, Aeroflex offers custom package development and package tooling modification ser-

vices for individual requirements. For ASIC's that require high signal I/O count, Aeroflex is developing flip chip packaging solu-

tions.

Note:

1.Contact Aeroflex for specific package drawings.

2. External chip capacitor attachment available to space quality levels (for improved SSO response).

3. Aeroflex supports all JEDEC outline package designs.

4. LGA package formats can be provided with Solder Columns.

EXTENSIVE CELL LIBRARY

The UT130nHBD ASIC family is supported by an extensive cell library that includes standard logic functions, Phase Lock Loop

(PLL) and SRAM with optional MBIST and EDAC. User-selectable options for cell configurations include scan and radiation hard-

ness (SEU) levels for all register elements, as well as output drive strength.

Phase-Locked Loop (PLL) macro cell is derived from the SerDes PLL and is capable of covering a frequency range of 100MHz to

500MHz. The PLL supports a power-down mode and phase lock indicator.

Refer to Aeroflex's UT130nHBD Design Manual for complete cell listing and details.

I/O BUFFERS

The UT130nHBD family offers a high number of specialized I/O's. For any specific design, signal availability is affected by pack-

age selection and IO type. The LVCMOS I/O cells can be configured by the user to serve as input, output, bidirectional or three-

state. Output drive options range from 4, 8, 12 and 24mA. To drive larger off-chip loads output drivers may be combined in parallel

to provide additional drive up to 48mA.

Other I/O buffer features and options include:

• Internally Configurable weak pull-up and pull-down devices

• Schmitt trigger

• LVDS

• HSTL

LVDS transmitter (Tx) and receiver (Rx) buffers are enhanced versions of the Aeroflex Standard Products UT54LVDS031LV

LVDS driver and UT54LVDS032LV receiver products. They provide the same >400Mbps (200MHz) switching rates, 340mV

nominal differential signaling levels, transmitter enable and receiver fail-safe circuitry. Each supports a power-down mode that

Table 2: Packaging

TYPE

TOTAL PINS

Flatpack

Up to 352

PGA

299

472,624