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configures the I/O buffers into their lowest power state. A unique Aeroflex reference circuit improves performance matching be-

tween multiple Tx buffers and multiple Rx buffers.

Aeroflex's ASIC HSTL bidirect, tristate and input buffers are based on the EIA/JEDEC Standard EIA/JESD8-6 (August 1995)

Class-1 and -2. They provide switching rates of 250MHz and all support a power-down mode.

JTAG BOUNDARY-SCAN

The UT130nHBD family allows for insertion of a test access port and boundary-scan that conforms to the IEEE Standard 1149.1

(JTAG). Some of the benefits of this capability are:

• Easy test of complex assembled printed circuit boards

• Gain access to and control of internal scan paths

• Initiation of Built-In Self Test

CLOCK DRIVER DISTRIBUTION

Aeroflex design tools provide methods for balanced clock distribution that maximize drive capability and minimize relative clock

skew between clocked devices.

SPEED AND PERFORMANCE

Aeroflex specializes in high-performance circuits designed to operate in harsh military and radiation environments.

Typically the propagation delay for a CMOS device is a function of its fanout loading, input slew, supply voltage, operating tem-

perature and processing radiation tolerance. In a radiation environment additional performance variances must be considered.

The UT130nHBD simulation models account for all of these effects to accurately determine circuit performance for its particular

set of use conditions.

POWER DISSIPATION

Power consumption of internal gates and I/O buffers is based on many factors including switching frequency, loading, voltage, tem-

perature and transistor leakage characteristics. Aeroflex's radiation-tolerant process exhibits power dissipation that is typical of

commercial CMOS processes. The UT130nHBD cell library supports a low power design methodology by providing high thresh-

old voltage VT versions of the core cells to reduce leakage current. Additionally the library contains clock gating cells that can be

used to reduce switching activity in designs. For rigorous power estimation methodology refer to the Aeroflex UT130nHBD Design

manual or consult with an Aeroflex Applications Engineer.

ASIC DESIGN SOFTWARE

Using a combination of state-of-the-art third-party and proprietary design tools Aeroflex delivers the CAE support and capability

to handle complex, high-performance ASIC designs from design concept through design verification and test.

Aeroflex's flexible circuit creation methodology supports high level design methodology by providing synthesis libraries in Liberty

syntax. Compiled technology files are provided for Synopsys synthesis and design analysis tools. Design verification is performed

in any VHDL or Verilog simulation environment using Aeroflex's robust libraries. Aeroflex also supports Automatic Test Program

Generation and Memory BIST to improve design testing.

AEROFLEX HDL DESIGN SYSTEMS

Aeroflex offers a Hardware Description Language (HDL) design system supporting both VHDL and Verilog that allows easy access

to Aeroflex's RadHard capabilities. Both the VHDL and Verilog libraries provide sign-off quality models and robust tools.