STA016T datasheet(18/45 Pages) STMICROELECTRONICS

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STA016T

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Description :

This register must contain a XDIV value that enables

the system PLL to generate a frequency of 50 MHZ

for the SYSCK. See table 4.

Default value at soft reset assume :

– external crystal provide a CRYCK running at

14.31818 MHz

PLL_SYSTEM_MDIV_50 :

Address : 0xEA (234)

Type : RW - DEC

Software Reset : 13

Description :

This register must contain a MDIV value that enables

the system PLL to generate a frequency of 50 MHz

for the SYSCK. See table 4.

Default value at soft reset assume :

– external crystal provide a CRYCK running at

14.31818 MHz

PLL_SYSTEM_PEL_42_5

Address : 0xE6 (230)

Type : RW - DEC

Software Reset : 126

Description :

This register must contain a PEL value that enables

the system PLL to generate a frequency of 42.5 MHz

for the SYSCK.See table 4.

Default value at soft reset assume :

– external crystal provide a CRYCK running at

14.31818 MHz

PLL_SYSTEM_PEH_42_5 :

Address : 0xE7 (231)

Type : RW - DEC

Software Reset : 223

Description :

This register must contain a PEH value that enables

the system PLL to generate a frequency of 42.5 MHz

for the SYSCK.See table 4.

Default value at soft reset assume :

– external crystal provide a CRYCK running at

14.31818 MHz

PLL_SYSTEM_NDIV_42_5 :

Address : 0xE8 (232)

Type : RW - DEC

Software Reset : 0

Description :

This register must contain a NDIV value that enables

the system PLL to generate a frequency of 42.5 MHz

for the SYSCK.See table 4.

Default value at soft reset assume :

– external crystal provide a CRYCK running at

14.31818 MHz

PLL_SYSTEM_XDIV_42_5 :

Address : 0xE9 (233)

Type : RW - DEC

Software Reset : 1

Description :

This register must contain a XDIV value that enables

the system PLL to generate a frequency of 42.5 MHz

for the SYSCK.See table 4.

Default value at soft reset assume :

– external crystal provide a CRYCK running at

14.31818 MHz

PLL_SYSTEM_MDIV_42_5 :

Address : 0xEA (234)

Type : RW - DEC

Software Reset : 10

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