STA016T datasheet(22/45 Pages) STMICROELECTRONICS

22 / 45 page

STA016T

22/45

Description :

If set to 1 enable the configurability of the CD & BS

input interfaces in audio mode thanks to following

registers, else disable this configurability and take

embedded default configuration.

Note that this embedded default configuration can be

retrieved by user thanks to following setting :

– I_AUDIO_CONFIG1 = b00010010;

// clocks in input

// & polarity negative

– I_AUDIO_CONFIG2 = b00110010;

// synchro with first data bit

// data unsigned, MSB first

– I_AUDIO_CONFIG3 = b11001111;

// LRCK phase length is 1

– I_AUDIO_CONFIG4 = b00000011;

// LRCK phase length is 16

– I_AUDIO_CONFIG5 = 0xFF;

// received 16 bits

– I_AUDIO_CONFIG6 = 0xFF;

// received 16 bits

– I_AUDIO_CONFIG7 = 0x00;

// received 16 bits

– I_AUDIO_CONFIG8 = 0x00;

// received 16 bits

– I_AUDIO_CONFIG9 = 16;

// data size is 16

– I_AUDIO_CONFIG10 = 0x00;

// no use because clock in input

– I_AUDIO_CONFIG11 = 0x00;

// no use because clock in input

_AUDIO_CONFIG_1 :

Address : 0x5B (91)

Type : RW - DEC

Software Reset : 0

Description :

If INPUT_CONF == 1, this register is used to config-

urate CD & BS input interfaces in audio mode.

_AUDIO_CONFIG_2 :

Address : 0x5C (92)

Type : RW - DEC

Software Reset : 0

Description :

If INPUT_CONF == 1, this register is used to config-

urate CD & BS input interfaces in audio mode.

CF7

CF6

CF5

CF4

CF3

CF2

CF1

CF0

Bit

Comment

CF0

Reserved : to be set to 0

CF1

Reserved : to be set to 1

CF2

Direction of bit clocks CD_BCK & BS_BCK:

0 : input

1 : output

CF3

Polarity of bit clocks CD_BCK & BS_BCK :

0 : data provided on falling edge & stable on

rising edge

1 : data provided on rising edge & stable on

falling edge

CF4

Reserved : to be set to 1

CF5

Direction of LR clocks CD_LRCK &

BS_LRCK :

0 : input

1 : output

CF6

Polarity of LR clocks CD_LRCK &

BS_LRCK :

0 : left sample corresponds to the low level

phase of LRCK

1 : left sample corresponds to the high level

phase of LRCK

CF7

Reserved : to be set to 0

CF15 CF14 CF13 CF12 CF11 CF10

CF9

CF8

Bit

Comment

CF8

Relative synchro :

0 : synchro with first data bit

1 : synchro one bit before first data bit

CF9

Data reception configuration :

0 : LSB first

1 : MSB first

CF10

Arithmetic type of the reception :

0 : unsigned data

1 : signed data

STA016T 데이터시트(PDF) 22 Page - STMicroelectronics

STA016T 데이터시트(HTML) 22 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

데이터시트 다운로드

링크 URL