ADA8282

Data Sheet

Rev. 0 | Page 6 of 21

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24 +OUTA

23 –OUTA

22 +OUTB

21 –OUTB

20 +OUTC

19 –OUTC

18 +OUTD

17 –OUTD

1

2

3

4

5

6

7

8

+INA

–INA

+INB

–INB

+INC

–INC

+IND

–IND

ADA8282

TOP VIEW

(Not to Scale)

NOTES

1. NIC = NO INTERNAL CONNECTION.

2. TIE THE EXPOSED PAD ON THE BOTTOM SIDE OF THE

PACKAGE TO THE ANALOG/DIGITAL GROUND PLANE.

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

0

EPAD

Exposed Pad. Tie the exposed pad on the bottom side of the package to the analog/digital ground plane.

1

+INA

Positive LNA Analog Input for Channel A.

2

−INA

Negative LNA Analog Input for Channel A.

3

+INB

Positive LNA Analog Input for Channel B.

4

−INB

Negative LNA Analog Input for Channel B.

5

+INC

Positive LNA Analog Input for Channel C.

6

−INC

Negative LNA Analog Input for Channel C.

7

+IND

Positive LNA Analog Input for Channel D.

8

−IND

Negative LNA Analog Input for Channel D.

9

AVDD

3.3 V Analog Supply.

10

NIC

No Internal Connection. Leave this pin floating.

11

NIC

No Internal Connection. Leave this pin floating.

12

NIC

No Internal Connection. Leave this pin floating.

13

NIC

No Internal Connection. Leave this pin floating.

14

NIC

No Internal Connection. Leave this pin floating.

15

NIC

No Internal Connection. Leave this pin floating.

16

AVDD

3.3 V Analog Supply.

17

−OUTD

Negative Analog Output for Channel D.

18

+OUTD

Positive Analog Output for Channel D.

19

−OUTC

Negative Analog Output for Channel C.

20

+OUTC

Positive Analog Output for Channel C.

21

−OUTB

Negative Analog Output for Channel B.

22

+OUTB

Positive Analog Output for Channel B.

23

−OUTA

Negative Analog Output for Channel A.

24

+OUTA

Positive Analog Output for Channel A.

25

AVDD

3.3 V Analog Supply.

26

VIO

Digital Level Select for SPI and RESET. This pin can accept 1.8 V to 3.3 V.

27

RESET

Reset Input. RESET overrides the SPI and powers down the device and returns all settings back to default. RESET is

pulled to ground by default. A logic high triggers the reset.

28

SCLK

Serial Clock.

29

CS

Chip Select Bar.

30

SDI

Serial Data Input.

31

SDO

Serial Data Output.

32

AVDD

3.3 V Analog Supply.