SP6120B datasheet(13/22 Pages) SIPEX

13 / 22 page

Date: 5/25/04

SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller

GATE DRIVER TEST CONDITONS

90%

10%

GH (GL)

NON-OVERLAP

RISE TIME

FALL TIME

90%

10%

V(BST)

Voltage

V(VCC)

Voltage

V(VCC = VIN)

SWN

Voltage

~0V

~V(Diode) V

~2V(VIN)

BST

Voltage

~V(VIN)

TIME

current valley and the reset pulse corresponding

to the end of an on-time indicates a current peak.

In effect, the main loop determines the status of

the secondary loop.

Notice that the output voltage appears to coast

toward the regulated value during periods where

the main loop would be telling the drivers to

switch. It is during this interval that the 3%

window comparator has taken control away from

the main loop. The main loop regains control

only if the output voltage crosses through its

regulated value. Also notice where the 3% com-

parator takes over. The output voltage is consid-

ered “high” only if the trough of the ripple is

above 3%. The output voltage is considered

“low” only if the peak of the ripple is below 3%.

By managing the secondary loop in this fashion,

the SP6120B can improve the transient response

of high performance power converters without

causing strange disturbances in low to moderate

performance systems.

Driver Logic

Signals from the PWM latch (QPWM), Fault

latch (FAULT), Program Logic, Zero Crossing

Comparator, and 3% Window Comparators all

flow into the Driver Logic. The following is a

truth table for determining the state of the GH and

GL voltages for given inputs:

100000000

000000

DDDD

XXXX

1111

The QPWM and 3% Comparators are grouped

together because 3% Low is the same as QPWM

= 1 and 3% High is the same as QPWM = 0.

Output Drivers

The driver stage consists of one high side, 4

Ω

driver, GH and one low side, 4

Ω, NFET driver,

GL. As previously stated, the high side driver can

be configured to drive a PFET or an NFET high

side switch. The high side driver can also be

configured as a switch node referenced driver.

Due to voltage constraints, this mode is mandatory

for 5V, single supply, high side NFET applica-

tions. The following figure shows typical driver

waveforms for the 5V, high side NFET design.

As with all synchronous designs, care must be

taken to ensure that the MOSFETs are properly

chosen for non-overlap time, peak current capa-

bility and efficiency.

Secondary Loop (3% Window Comparator):

continued

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