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Date: 05/25/04

SP6654 High Efficiency 800mA Synchronous Buck Regulator

© Copyright 2004 Sipex Corporation

blank the loop comparator from starting a new

charge cycle for a minimum period. This blank-

ing period occurs during the noisy LX transition

to discharge, where spurious comparator states

discharge or wait state until the loop comparator

starts the next charge cycle by DRVON going

high.

If an over current occurs during charge the loop

is interrupted and DRVON is RESET. The off-

for that time. At the end of the off-time the loop

is released and controlled by VOLOW. In this

manner maximum inductor current is controlled

on a cycle-by-cycle basis. An assertion of UVLO

(undervoltage lockout) or TSD (thermal shut-

down) holds the loop in no-charge until the fault

has ended.

On-Time Control - Discharge Phase

The discharge phase follows with the high side

PMOS switch opening and the low side NMOS

switch closing to provide a discharge path for

the inductor current. The decreasing inductor

current and the load current cause the output

voltage to drop. Under normal load conditions

when the inductor current is below the pro-

grammed limit, the off-time will continue until

the output voltage falls below the regulation

threshold, which initiates a new charge cycle via

the loop comparator.

The inductor current “floats” in continuous con-

duction mode. During this mode the inductor

peak current is below the programmed limit and

the valley current is above zero. This is to satisfy

load currents that are greater than half the mini-

defined by the equation:

*

L

where:

L = Inductor value

to:

L

For most applications, the inductor current ripple

controlled by the SP6654 is constant regardless

of input and output voltage. Because the output

voltage ripple is equal to:

where:

the output ripple of the SP6654 regulator is

independent of the input and output voltages.

For battery powered applications, where the

battery voltage changes significantly, the SP6654

provides constant output voltage ripple through-

out the battery lifetime. This greatly simplifies

the LC filter design.

The maximum loop frequency in CCM is de-

fined by the equation:

where:

Ignoring conduction losses simplifies the loop

frequency to:

1

*

AND’ing the loop comparator and the on-timer

reduces the switching frequency for load cur-

rents below half the inductor ripple current. This

increases light load efficiency. The minimum

on-time insures that the inductor current ripple

OPERATION: Continued