6

Rev:A Date: 11/20/03

SP6681 High Efficiency Boost Charge Pump Regulator

© Copyright 2002 Sipex Corporation

4) The Clock Phase Control accepts the clock

and mode control generated by the Clock Manager

and the Charge Pump Switch Configuration

Control. This block then provides several clock

phases going to the Drivers block.

5) The V

Control to ensure V

6) The Drivers block drives the clock phase

information to the gates of the large pump

transistors.

7) The Charge Pump Switch block contains the

large transistors that transfer charge to the fly

and load capacitors.

In normal operation of the device V

between +2.7 and 5.5V. Refer to Figure 2 for a

typical application circuit. When no clock is

present (CLK is floating or near ground) the

device is in shutdown and the output is connected

to the input. This shutdown feature will work

either in start up or after the device is pumping.

Once a clock is present, the band gap is activated,

but only if V

Otherwise the device

remains in shutdown mode. Once the reference

voltage is stable, the device begins the pumping

operation.

If V

doubler. However, as the output reaches 5.0V,

the doubler action is truncated.

If V

and multiplies the input by a factor of 1.5. This

mode reduces the current drawn from the supply

and hence increases the power efficiency. As the

output reaches 5.0V, the charge transfer to the

load capacitor is truncated.

APPLICATION INFORMATION

Refer to Figure 3 for a typical SIM card

application circuit with the SP6681.

Oscillator Control

The external clock frequency required to drive

the internal charge pump oscillator is 32.768kHz

(nominal) at the CLK pin. When there is no

clock signal present at the CLK pin, the SP6681

device is in a low-power shutdown mode.

C/4 and Cx8 are two control lines for the internal

charge pump oscillator. When the C/4 control

line is forced to a logic high and the Cx8 control

line is at a low, the internal charge pump oscillator

is set to 8.192kHz. When both the C/4 and Cx8

control lines are at a logic low, the internal

charge pump oscillator is set to the input clock

signal, 32.768kHz. When the C/4 control line is

forced to a logic high, the internal charge pump

oscillator is set to 262.14kHz.

Figure 2. Typical Application for the SP6681

CF1P

CF1N

GND

SP6681

5

3

2

1

4

CF1 = 2.2µF

C/4

Cx8

Frequency

Control

Inputs

CF2N

CF2P

CLK

10

9

8

7

6

CF2 = 2.2µF

Input Clock

2.7V to 5.5V

5.0V