M08045 datasheet(35/49 Pages) MA-COM

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Functional Description

M08035, M08045 Data Sheet V1

MACOM

™

080x5-DSH-001

4.9.1

Reading Register Alarm Bits

The LOS and LOL alarm bits are latched when asserted. After reading they should be cleared using the CLRALRM

bit in register 88h. This bit needs to be set to '1' to reset the alarms. It should then be reset to a '0' to re-enable

normal alarm operation.

4.10

Internal Regulator

Both digital and analog cores of the M08035/M08045 are designed to run from a 1.2 V supply. If a 1.2 V supply is

not available locally, then the internal regulator can be used to create this domain from AVDDI/AVDDO and DVDDIO.

Setting the xREG_EN pin LOW, enables the internal regulator. This regulator generates a 1.2 V domain at pins

AVDD and DVDD. See Figure 4-10 through Figure 4-12 for the three different supply configurations. Note that the

decoupling capacitors should be at least 100 nF.

When the internal regulator is used, all the current for the device is taken through the AVDDI/AVDDO and DVDDIO

pins. Because of this, care should be taken to ensure that the supplies to these pins are sufficient to handle the

total current.

Figure 4-9.

xALARM-Output Interrupt Mode

LOS

LOL

xALARM

Interrupt occurs when LOS or LOL changes state.

xALARM pulse width is programmable.

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