PI7C7300D datasheet(49/107 Pages) PERICOM

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PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 49 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C7300D behaves in

the same way as if only the VGA mode bit were set.

TRANSACTION ORDERING

To maintain data coherency and consistency, PI7C7300D complies with the ordering

rules set forth in the PCI Local Bus Specification, Revision 2.2, for transactions crossing

the bridge. This chapter describes the ordering rules that control transaction forwarding

across PI7C7300D.

6.1

TRANSACTIONS GOVERNED BY ORDERING RULES

Ordering relationships are established for the following classes of transactions crossing

PI7C7300D:

Posted write transactions, comprised of memory write and memory write and

invalidate transactions.

Posted write transactions complete at the source before they complete at the destination;

that is, data is written into intermediate data buffers before it reaches the target.

Delayed write request transactions, comprised of I/O write and configuration write

transactions.

Delayed write requests are terminated by target retry on the initiator bus and are queued

in the delayed transaction queue. A delayed write transaction must complete on the target

bus before it completes on the initiator bus.

Delayed write completion transactions, comprised of I/O write and configuration

write transactions.

Delayed write completion transactions complete on the target bus, and the target response

is queued in the buffers. A delayed write completion transaction proceeds in the direction

opposite that of the original delayed write request; that is, a delayed write completion

transaction proceeds from the target bus to the initiator bus.

Delayed read request transactions, comprised of all memory read, I/O read, and

configuration read transactions.

Delayed read requests are terminated by target retry on the initiator bus and are queued in

the delayed transaction queue.

Delayed read completion transactions, comprised of all memory read, I/O read, &

configuration read transactions.

Delayed read completion transactions complete on the target bus, and the read data is

queued in the read data buffers. A delayed read completion transaction proceeds in the

direction opposite that of the original delayed read request; that is, a delayed read

completion transaction proceeds from the target bus to the initiator bus.

PI7C7300D does not combine or merge write transactions:

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