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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MB9B520M 데이터시트(PDF) 69 Page - SPANSION |
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MB9B520M 데이터시트(HTML) 69 Page - SPANSION |
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69 / 113 page  D a t a S h e e t 66 MB9B520M_DS706-00048-3v0-E, March 18, 2015 CONFIDENTIAL (4-1) Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time* 1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiplication rate - 5 - 37 multiplier PLL macro oscillation clock frequency fPLLO 75 - 150 MHz Main PLL clock frequency* 2 fCLKPLL - - 72 MHz USB clock frequency* 3 fCLKSPLL - - 48 MHz After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". *3: For more information about USB clock, see "Chapter 2-2: USB Clock Generation" in "FM3 Family PERIPHERAL MANUAL Communication Macro Part". (4-2) Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time* 1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate - 19 - 35 multiplier PLL macro oscillation clock frequency fPLLO 72 - 150 MHz Main PLL clock frequency* 2 fCLKPLL - - 72 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". Note: Make sure to input to the Main PLL source clock, the high-speed CR clock (CLKHC) that the frequency/temperature has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Main clock (CLKMO) K divider PLL input clock USB PLL M divider USB clock N divider USB PLL connection PLL macro oscillation clock K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Main PLL connection |
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