MB91F528 datasheet(208/241 Pages) SPANSION

208 / 241 page

D a t a S h e e t

March 28, 2014, MB91F528_DS705-00016-1v0-E

205

CONFIDENTIAL

(4-4) I

2C timing

(TA: -40°C to +125°C,VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)

Parameter

Sym

bol

Pin name

Conditio

Standard

mode

High-speed

mode*

Unit

Rem

arks

Min

Max

Min

Max

SCL clock frequency

fSCL

SCK3 to SCK8,

SCK11 to SCK19

CL=50pF

(VP/IOL)

100

400

kHz

Repeat "start"

condition hold time

SDA ↓ → SCL ↓

tHDSTA

SOT3 to SOT8,

SOT11 to SOT19

(SDA),

SCK3 to SCK8,

SCK11 to SCK19

(SCL)

4.0

–

0.6

–

μs

Period of "L" for SCL

clock

tLOW

SCK3 to SCK8,

SCK11 to SCK19

(SCL)

4.7

–

1.3

–

μs

Period of "H" for SCL

clock

tHIGH

SCK3 to SCK8,

SCK11 to SCK19

(SCL)

4.0

–

0.6

–

μs

Repeat "start"

condition setup time

SCL ↑ → SDA ↓

tSUSTA

SCK3 to SCK8,

SCK11 to SCK19

(SCL)

4.7

–

0.6

–

μs

Data hold time

SCL ↓ → SDA ↓ ↑

tHDDAT

SOT3 to SOT8,

SOT11 to SOT19

(SDA)

SCK3 to SCK8,

SCK11 to SCK19

(SCL)

3.45

0.9

μs

Data setup time

SDA ↓ ↑ → SCL ↑

tSUDAT

SOT3 to SOT8,

SOT11 to SOT19

(SDA)

SCK3 to SCK8,

SCK11 to SCK19

(SCL)

250

–

100

–

"Stop" condition setup

time

SCL ↑ → SDA ↑

tSUSTO

SOT3 to SOT8,

SOT11 to SOT19

(SDA)

SCK3 to SCK8,

SCK11 to SCK19

(SCL)

4.0

–

0.6

–

μs

Bus-free time between

"stop" condition and

"start" condition

tBUF

–

4.7

–

1.3

–

μs

Noise filter

tSP

–

2tCPP

–

2tCPP

–

Notes: Only ch.3, ch.4 and ch.12-ch.19 are standard mode/high-speed mode correspondence. In ch.5-ch.8 and

ch.11, only a standard mode is correspondences.

*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines,

respectively.

Vp shows that the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.

*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.

*3: A high-speed mode I

2C bus device can be used on a standard mode I2C bus system as long as the device

satisfies the requirement of "tSUDAT ≥ 250 ns".

*4: tCPP is the peripheral clock cycle time. Adjust the clock of the bus in the surrounding to 8MHz or more when

use I

2C.

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