ADC12L032CIWM datasheet(29/36 Pages) NSC

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Application Hints (Continued)

3.0 REFERENCE VOLTAGE

The difference in the voltages applied to the V

REF

+ and

REF

− defines the analog input span (the difference between

the voltage applied between two multiplexer inputs or the

voltage applied to one of the multiplexer inputs and analog

ground), over which 4095 positive and 4096 negative codes

exist. The voltage sources driving V

REF

+ or V

REF

− must have

very low output impedance and noise.

The ADC12L030/2/4/8 can be used in either ratiometric or

absolute reference applications. In ratiometric systems, the

analog input voltage is proportional to the voltage used for

the ADC’s reference voltage. When this voltage is the sys-

tem power supply, the V

REF

+ pin is connected to V

+ and

REF

− is connected to ground. This technique relaxes the

system reference stability requirements because the analog

input voltage and the ADC reference voltage move together.

This maintains the same output code for given input condi-

tions. For absolute accuracy, where the analog input voltage

varies between very specific voltage limits, a time and tem-

perature stable voltage source can be connected to the ref-

erence inputs. Typically, the reference voltage’s magnitude

will require an initial adjustment to null reference voltage in-

duced full-scale errors.

Below are recommended references along with some key

specifications.

Output

Temperature

Part Number

Voltage

Coefficient

Tolerance

(max)

LM4041CIM3-Adj

±0.5%

±100ppm/˚C

LM4040AIM3-2.5

±0.1%

±100ppm/˚C

The reference voltage inputs are not fully differential. The

ADC12L030/2/4/8 will not generate correct conversions or

comparisons if V

REF

+ is taken below V

REF

−. Correct conver-

sions result when V

REF

+ and V

REF

− differ by 1V and remain,

at all times, between ground and V

+. The V

REF common

mode range, (V

REF

+ +V

REF

−)/2, is restricted to (0.1 x V

+)to

(0.6 x V

+). Therefore, with V

+ = 3.3V the center of the ref-

erence ladder should not go below 0.33V or above 1.98V.

Figure 15 is a graphic representation of the voltage restric-

tions on V

REF

+ and V

REF

−.

DS011830-50

FIGURE 14. Fully Differential Biasing

DS011830-43

FIGURE 15. V

REF Operating Range

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