ADC12L032CIWM datasheet(8/36 Pages) NSC

8 / 36 page

AC Electrical Characteristics

The following specifications apply for V

+ = V

A+ = VD+ = +3.3 VDC,VREF+ = +2.500 VDC,VREF− = 0VDC, 12-bit + sign conver-

sion mode, t

r = tf = 3 ns, fCK = fSK = 5 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input

with fixed 1.250V common-mode voltage, and 10(t

CK) acquisition time unless otherwise specified. Boldface limits apply for TA

= T

J = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Note 17)

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 10)

(Note 11)

(Limits)

Conversion Clock (CCLK) Frequency

MHz (max)

MHz (min)

Serial Data Clock SCLK Frequency

MHz (max)

Hz (min)

Conversion Clock Duty Cycle

% (min)

% (max)

Serial Data Clock Duty Cycle

% (min)

% (max)

Conversion Time

12-Bit + Sign or 12-Bit

44(t

CK)

44(t

CK)

(max)

8.8

µs (max)

8-Bit + Sign or 8-Bit

21(t

CK)

21(t

CK)

(max)

4.2

µs (max)

Acquisition Time

6 Cycles Programmed

6(t

CK)

6(t

CK)

(min)

(Note 19)

7(t

CK)

(max)

1.2

µs (min)

1.4

µs (max)

10 Cycles Programmed

10(t

CK)

10(t

CK)

(min)

11(t

CK)

(max)

2.0

µs (min)

2.2

µs (max)

18 Cycles Programmed

18(t

CK)

18(t

CK)

(min)

19(t

CK)

(max)

3.6

µs (min)

3.8

µs (max)

34 Cycles Programmed

34(t

CK)

34(t

CK)

(min)

35(t

CK)

(max)

6.8

µs (min)

7.0

µs (max)

CAL

Self-Calibration Time

4944(t

CK)

4944(t

CK)

(max)

988.8

µs (max)

Auto-Zero Time

76(t

CK)

76(t

CK)

(max)

15.2

µs (max)

SYNC

Self-Calibration or Auto-Zero

2(t

CK)

2(t

CK)

(min)

Synchronization Time

3(t

CK)

(max)

from DOR

0.40

µs (min)

0.60

µs (max)

DOR

DOR High Time when CS is Low

Continuously

9(t

SK)

9(t

SK)

(max)

for Read Data and Software Power

Up/Down

1.8

µs (max)

CONV

CONV Valid Data Time

8(t

SK)

8(t

SK)

(max)

1.6

µs (max)

HPU

Hardware Power-Up Time, Time from

250

700

µs (max)

PD Falling Edge to EOC Rising Edge

ADC12L032CIWM 데이터시트(PDF) 8 Page - National Semiconductor (TI)

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