PIC16F876ATISLASHML datasheet(30/234 Pages) MICROCHIP

30 / 234 page

PIC16F87XA

DS39582B-page 28

 2003 Microchip Technology Inc.

2.2.2.7

PIR2 Register

The PIR2 register contains the flag bits for the CCP2

interrupt, the SSP bus collision interrupt, EEPROM

write operation interrupt and the comparator interrupt.

PIR2 REGISTER (ADDRESS 0Dh)

Note:

Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable

bit,

GIE

(INTCON<7>).

User

software should ensure the appropriate

interrupt flag bits are clear prior to

enabling an interrupt.

U-0

R/W-0

U-0

R/W-0

U-0

R/W-0

—CMIF

—

EEIF

BCLIF

—

CCP2IF

bit 7

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6

CMIF: Comparator Interrupt Flag bit

= The comparator input has changed (must be cleared in software)

= The comparator input has not changed

bit 5

Unimplemented: Read as ‘0’

bit 4

EEIF: EEPROM Write Operation Interrupt Flag bit

= The write operation completed (must be cleared in software)

= The write operation is not complete or has not been started

bit 3

BCLIF: Bus Collision Interrupt Flag bit

= A bus collision has occurred in the SSP when configured for I2C Master mode

= No bus collision has occurred

bit 2-1

Unimplemented: Read as ‘0’

bit 0

CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare mode:

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode:

Unused.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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