PIC16F876ATISLASHML datasheet(78/234 Pages) MICROCHIP

78 / 234 page

PIC16F87XA

DS39582B-page 76

 2003 Microchip Technology Inc.

9.3.5

MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 9-2) is to

broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SDO output could be

disabled (programmed as an input). The SSPSR

SDI pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

The clock polarity is selected by appropriately program-

ming the CKP bit (SSPCON<4>). This then, would give

waveforms for SPI communication as shown in

Figure 9-3, Figure 9-5 and Figure 9-6, where the MSB

is transmitted first. In Master mode, the SPI clock rate

(bit rate) is user programmable to be one of the

following:

•FOSC/4 (or TCY)

•FOSC/16 (or 4 • TCY)

•FOSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum data rate (at 40 MHz) of

10.00 Mbps.

Figure 9-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

FIGURE 9-3:

SPI MODE WAVEFORM (MASTER MODE)

SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDI

bit 7

bit 0

SDO

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

bit 7

bit 0

SDI

SSPIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

SDO

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

(CKE = 0)

(CKE = 1)

Next Q4 Cycle

after Q2

↓

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