PC87413 datasheet(245/257 Pages) NSC

245 / 257 page

11.0 Device Characteristics (Continued)

Revision 1.2

245

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11.5.5

X-Bus Extension Timing (PC87416 and PC87417)

Symbol

Figure

Description

Reference Conditions

Min

Max

Unit

tVAL

Outputs

Output Valid Delay

After RE Internal Clock

201

1. Not tested. Guaranteed by characterization.

tON

Outputs

Float to Active Delay

After RE Internal Clock

2. Not tested. Guaranteed by design.

tOH

Outputs

Output Hold time

After RE Internal Clock

tOFF

Outputs

Active to Float Delay

After RE Internal Clock

301

tSU

Inputs

Input Setup Time

Before RE Internal Clock

151

tHL

Inputs

Input Hold Time

After RE Internal Clock

tCSDV

Mode 0 Turbo

Read Transaction

Chip Select active to Data Valid Read from External Device

tON

Outputs

tVAL

tOFF

XRD_XEN, XWR_XRW,

(for reference only;

XA11-0, XD7-0,

Internal Clock

tOH

not available off chip)

XSTB2-0, XCS3-0

Internal Clock

XD7-0

tSU

tHL

Input

Valid

Inputs

(for reference only:

XRDY, XIRQ

not available off chip)

XD7-0

tCSDV

Data

Valid

Mode 0 Turbo Read Transaction

XCS3-0

PC87413 데이터시트(PDF) 245 Page - National Semiconductor (TI)

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