PC87413 datasheet(56/257 Pages) NSC

56 / 257 page

3.0 Device Architecture and Configuration (Continued)

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Revision1.2

3.7.10

Clock Generator Configuration Register (CLOCKCF)

Power Well:VSB

Location:Index 29h

Type:

Varies per bit

Bit

43210

Name

LOCKCCF

LFCKSEL

HFCKDIS

CKVALID

CKIN48

HFCKDIV

Reset

Strap

See Table

Bit

Type

Description

R/W1S LOCKCCF (Lock Clock Configuration). When set to 1, this bit locks the conﬁguration register

CLOCKCF by disabling writing to all its bits (including to the LOCKCCF bit itself). Once set, this bit can

be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up reset, according to

the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 128). In addition, this bit is

cleared by setting the UNLOCKC bit in the ACBLKCTL register (PC87413 and PC87417).

0: R/W bits are enabled for write (default)

1: All bits are RO

R/W or

LFCKSEL (Low Frequency Clock Select). Selects the frequency generated at the LFCKOUT pin.

0: 32.768 KHz (default)

1: 1 Hz

R/W or

HFCKDIS (High Frequency Clock Disable). Disables both the HFCKOUT output and the

programmable divider to save power.

0: Enabled (default)

1: Disabled (set low)

4RO

CKVALID (Valid Multiplier Clock Status). This bit indicates the status of output from the Frequency

Multiplier (the internal clock signal).

0: Internal clock frozen (default)

1: Internal clock active (stable and toggling)

3RO

CKIN48 (Clock Input Available). This bit indicates the value of the CKIN48 strap input, sampled at VSB

Power-Up reset.

0: No clock is available at the CLKIN pin (pin 56 connected to GPIO55)

1: A 48 MHz clock is available at the CLKIN pin (pin 56 connected to CLKIN)

2-0

R/W or

HFCKDIV (High Frequency Clock Divisor). These bits deﬁne the value by which the 48 MHz or 40

MHz internal clock frequency is divided to generate the HFCKOUT signal. The resulting frequency

depends on the value of the CKIN48 bit (see Table 7 on page 37).

Bits

2 1 0

Function

0 0 0:

Divide by 1 (default for CKIN48 = 1)

0 0 1:

Divide by 2 (default for CKIN48 = 0)

0 1 0:

Divide by 3

0 1 1:

Divide by 4

1 0 0:

Divide by 6

1 0 1:

Divide by 8

1 1 0:

Divide by 12

1 1 1:

Divide by 16

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