PC87413 datasheet(101/257 Pages) NSC

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5.0 X-Bus Extension (Continued)

Revision 1.2

101

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Figure 22. Mode 1, Normal Address X-Bus Transaction - Write Access Cycle

5.2.9

Latched Address Mode X-Bus Transactions

The read and write transactions in Latched Address mode are similar to those used in Normal Address mode except for the

way the addresses are placed on the X-Bus. In Latched Address mode, address signals 27-0 are output using the XA signals

via multiplexing over the data bus (XD7-0). The purpose of Latch control signals XSTB2-0 is to separate the XA signals from

the XD7-0 data bus. The XSTB2-0 signals are active from the time the address signals are valid (and until the end of a trans-

action).

Latched address X-Bus transactions are available at two levels:

Standard - standard access time transactions available in mode 0, mode 0 fast, and mode 1.

Turbo - low access time transactions available in mode 0 turbo.

Standard Read Transactions. When a read cycle on the LPC falls within any of the enabled X-Bus decoded address rang-

es (or an indirect read is started or an X-Bus read through the ACCESS.bus is started), a read cycle begins. A read cycle

starts by outputting the lower 12 address signals on address signals XA11-0 and by outputting address lines 27-20 on data

signals XD7-0 on the rising edge of the clock. Two CLK cycles later, a strobe signal (XSTB2) is asserted to latch the address

in an external latch. Two CLK cycles later, a second set of address lines (19-12) is placed on data pins XD7-0. These can

be latched by the strobe signal XSTB1 asserted two cycles later on the rising edge of the clock. Two CLK cycles later, the

last group of address lines (11-4) is placed on data signals XD7-0. The XSTB0, asserted two cycles later on the rising edge

of the clock, can be used to latch this part of the address. Two CLK cycles later on the rising edge of the clock, the PC8741x

stops driving the data bus. At this point, all addresses are available either at the address outputs of the PC8741x (XA11-0)

or in the three latches. The system may require only part of these addresses, depending on the size of the memory or pe-

ripheral address space. One CLK cycle later, either a chip-select signal XCSn or the enable signal XRD_XEN is asserted,

based on the XCSn mode setting (where n is a chip-select number from 0 to 3, based on the address accessed and the

select signal mapping). From this point, the read continues as described for the Normal Address mode. XSTB2-0 are de-

asserted one CLK cycle after the de-assertion of XCSn. At this time, the latched address becomes invalid.

CLK

(Internal; for Reference Only)

XD7-0

XA11-0

XCSn

XWR_XRW

XRD_XEN

Insert: 16 + “Programmed Wait States” CLK cycles.

During this time, non-clock signals do not change.

Insert: 8 CLK cycles.

PC87413 데이터시트(PDF) 101 Page - National Semiconductor (TI)