CS5530 datasheet(105/241 Pages) NSC

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Functional Description (Continued)

3.6

IDE CONTROLLER

The CS5530 integrates a fully-buffered, 32-bit, ANSI ATA-

4-compliant (Ultra DMA/33) IDE interface. The IDE inter-

face supports two channels, primary and secondary, each

supporting two devices that can operate in PIO Modes 1,

2, 3, 4, Multiword DMA, or Ultra DMA/33.

The IDE interface provides a variety of features to opti-

mize system performance, including 32-bit disk access,

post write buffers, bus master, Multiword DMA, look-

ahead read buffer, and prefetch mechanism for each

channel respectively.

The IDE interface timing is completely programmable.

Timing control covers the command active and recover

pulse widths, and command block register accesses. The

IDE data-transfer speed for each device on each channel

can be independently programmed allowing high-speed

IDE peripherals to coexist on the same channel as older,

compatible devices.

The CS5530 also provides a software-accessible buffered

reset signal to the IDE drive, F0 Index 44h[3:2] (Table 3-

53). The IDE_RST# signal is driven low during reset to the

CS5530 and can be driven low or high as needed for

device-power-off conditions.

3.6.1

IDE Interface Signals

The CS5530 has two completely separate IDE control sig-

nals, however, the IDE_RST#, IDE_ADDR[2:0] and

IDE_DATA[15:0] are shared. The connections between

the CS5530 and IDE devices are shown as Figure 3-19.

Figure 3-19. CS5530 and IDE Channel Connections

Table 3-53. IDE Reset Bits

Bit

Description

F0 Index 44h

Reset Control Register (R/W)

Reset Value = xx000000b

IDE Controller Reset: Reset the IDE Controller: 0 = Disable; 1 = Enable.

Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

IDE Reset: Reset IDE bus: 0 = Disable; 1 = Enable.

Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

IDE_ADDR[2:0]

IRQ14

IRQ15

IDE_DATA[15:0]

Primary

Channel

Secondary

Channel

IDE_RST#

IDE_CS0#, IDE_DREQ0,

IDE_DACK0#, IDE_IORDY0,

IDE_IOR0#, IDE_IOW0#

IDE_CS1#, IDE_DREQ1,

IDE_DACK1#, IDE_IORDY1,

IDE_IOR1#, IDE_IOW1#

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