CS5530 datasheet(211/241 Pages) NSC

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Revision 4.1

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Table 4-26. DMA Page Registers

Bit

Description

I/O Port 081h (R/W)

DMA Channel 2 Low Page Register

Address bits [23:16] (byte 2).

I/O Port 082h (R/W)

DMA Channel 3 Low Page Register

Address bits [23:16] (byte 2).

I/O Port 083h (R/W)

DMA Channel 1 Low Page Register

Address bits [23:16] (byte 2).

I/O Port 087h (R/W)

DMA Channel 0 Low Page Register

Address bits [23:16] (byte 2).

I/O Port 089h (R/W)

DMA Channel 6 Low Page Register

Address bits [23:16] (byte 2).

I/O Port 08Ah (R/W)

DMA Channel 7 Low Page Register

Address bits [23:16] (byte 2).

I/O Port 08Bh (R/W)

DMA Channel 5 Low Page Register

Address bits [23:16] (byte 2).

I/O Port 08Fh (R/W)

ISA Refresh Low Page Register

Refresh address.

I/O Port 481h (R/W)

DMA Channel 2 High Page Register

Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 081h.

I/O Port 482h (R/W)

DMA Channel 3 High Page Register

Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 082h.

I/O Port 483h (R/W)

DMA Channel 1 High Page Register

Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 083h.

I/O Port 487h (R/W)

DMA Channel 0 High Page Register

Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 087h.

I/O Port 489h (R/W)

DMA Channel 6 High Page Register

Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 089h.

I/O Port 48Ah (R/W)

DMA Channel 7 High Page Register

Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 08Ah.

I/O Port 48Bh (R/W)

DMA Channel 5 High Page Register

Address bits [31:24] (byte 3). Note: This register is reset to 00h on any access to Port 08Bh.

CS5530 데이터시트(PDF) 211 Page - National Semiconductor (TI)

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