NJM431S/NJM432S

- 2 -

Ver.2015-06-26

■ ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MAXIMUM RATINGS

UNIT

Cathode Voltage

37 (*1)

V

Continuous Cathode Current

-100 to 150

mA

Reference Input Current

-0.05 to 10

mA

Power Dissipation

SOT-89-3 : 450(*2)

: 1300(*3)

mW

SOT-23-5 : 480(*4)

: 650(*5)

Operating Temperature Range

-40 to +125

C

Storage Temperature Range

-50 to +150

C

(*1) Unless specified, all voltage value are with respect to the anode pin.

(*2) Mounted on glass epoxy board. (76.2

(*3) Mounted on glass epoxy board. (76.2

 114.3  1.6mm: EIA/JDEC standard size, 4Layers)

(4Layers inner foil: 74.2

 74.2mm applying a thermal via hole to a board based on JEDEC standard JESD51-5)

(*4) Mounted on glass epoxy board based on EIA/JEDEC. (76.2

 114.3  1.6mm: 2Layers FR-4)

(*5) Mounted on glass epoxy board based on EIA/JEDEC. (76.2

 114.3  1.6mm: 4Layers FR-4),

internal Cu area: 74.2

 74.2mm

■ RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Cathode Voltage

-

36

V

Cathode Current

0.7

-

100

mA

■ ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Reference Voltage

2450

2495

2540

mV

Reference Input Voltage Change

Over Temperature Range

∆V

REF

(dev)

-

8

17

mV

Reference Voltage Change

vs. Cathode Voltage Change

∆V

∆V

KA

(*7)

∆V

∆V

-

-1.4

-1

-2.7

-2

mV/V

Reference Input Current

R1=10k

Ω, R2=∞(*7)

-

2

4

µA

Reference Input Current Change

Over Temperature Range

∆I

REF

(dev)

R1=10k

Ω, R2=∞(*7)

-

0.4

1.2

µA

Minimum Cathode Current

-

0.4

0.7

mA

OFF State Cathode Current

-

0.1

1.0

µA

Dynamic Impedance

ΙZ

f

≤1kHz(*6)

-

0.2

0.5

Ω

The maximum value of

“Dynamic Impedance“, “Reference Voltage Change” and “Reference Input Current Change”

are determined based on sampling evaluation from the initial production lots, and thus not tested in the production test.

Therefore, these values are for the reference design purpose only.

(*6) Test Circuit Fig.1

(*7) Test Circuit Fig.2

(*8) Test Circuit Fig.3