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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADC12DL040CIVS/NOPB 데이터시트(PDF) 17 Page - Texas Instruments |
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ADC12DL040CIVS/NOPB 데이터시트(HTML) 17 Page - Texas Instruments |
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17 / 37 page  ADC12DL040 www.ti.com SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, VREF = +1.0V, fCLK = 40 MHz, fIN = 20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C SNR,SINAD,SFDR vs. fCLK Distortion vs. fCLK Figure 19. Figure 20. SNR,SINAD,SFDR vs. Clock Duty Cycle Distortion vs. Clock Duty Cycle Figure 21. Figure 22. SNR,SINAD,SFDR vs. VREF Distortion vs. VREF Figure 23. Figure 24. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: ADC12DL040 |
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