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ADC12DL040CIVS/NOPB 데이터시트(PDF) 3 Page - Texas Instruments |
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ADC12DL040CIVS/NOPB 데이터시트(HTML) 3 Page - Texas Instruments |
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3 / 37 page ![]() Output Buffers MUX Duty Cycle Stabilizer Digital Correction Output Buffers Digital Correction 12 OEA OEB DB1-DB11 12 11 DA0-DA11 or D0-D11 (MUX) DB0/ABb 21 2 Stage 1 Stage 10 Stage 9 Stage 8 Stage 3 Stage 2 S/H Timing Control 2 10-Stage Pipeline Converter 2 2 2 3 2 2 2 2 2 2 2 Stage 1 Stage 10 Stage 9 Stage 8 Stage 3 Stage 2 S/H Timing Control 2 10-Stage Pipeline Converter 2 2 2 3 2 2 2 2 2 2 2 Internal Reference Reference Select 2 MULTIPLEX 21 12 VINA+ VINA- VINB- VINB+ VRPA VRMA VRNA VRPB VRMB VRNB CLK VREF ADC12DL040 www.ti.com SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013 Block Diagram Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC12DL040 |
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