ADC12DL080CIVSSLASHNOPB datasheet(5/34 Pages) TI1

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AGND

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AGND

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AGND

ADC12DL080

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SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013

Pin Descriptions and Equivalent Circuits (continued)

Pin No.

Symbol

Equivalent Circuit

Description

DIGITAL I/O

Digital clock input. The range of frequencies for this input is as

CLK

specified in the electrical tables with ensured performance at 80

MHz. The inputs are sampled on the rising edge.

OF/DOEN selects the output format (OF) or enables the DRDY

output (DOEN). The state of this pin also controls the function of pins

22 and 41.

When OF/DOEN is tied to VRMA or VRMB, DRDY is enabled. Pin 41

is used as the DRDY output strobe, and pin 22 is used to select the

OF/DOEN

output format. Output Enable for channels A and B are not available

in this mode.

When OF/DOEN is LOW, the output data format is offset binary.

With OF/DOEN tied HIGH, the output format is 2's complement.

See Table 4 in OF/DOEN, OEA/OF, and OEB/DRDY for more

information.

Output Enable for Channel A (OEA ) or Output format (OF). The

function of this pin is controlled by the state of pin 21.

When DRDY is enabled (pin 21 tied to VRMA or VRMB) this pin sets

the output format. When LOW, the output data format is offset

binary. When HIGH, the output format is 2's complement.

OEA/OF

When DRDY is not enabled (pin 21 is LOW or HIGH) this pin is the

Output Enable for Channel A. When LOW the outputs for Channel A

are active. When HIGH, the outputs for Channel A are in a high

impedance state.

See Table 4 in OF/DOEN, OEA/OF, and OEB/DRDY for more

information.

Output Enable for Channel B (OEB ) or Data Ready Output strobe

(DRDY). The function of this pin is controlled by the state of pin 21.

When DRDY is enabled (pin 21 tied to VRMA or VRMB) this pin is the

DRDY output. The data outputs are synchronized with the falling

edge of this signal. This signal switches at the same rate as the input

clock.

OEB/DRDY

When DRDY is not enabled (pin 21 is LOW or HIGH) this pin is the

Output Enable for Channel B. When LOW the outputs for Channel B

are active. When HIGH, the outputs for Channel B are in a high

impedance state.

See Table 4 in OF/DOEN, OEA/OF, and OEB/DRDY for more

information.

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