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ADS5541IPAPR 데이터시트(PDF) 7 Page - Texas Instruments |
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ADS5541IPAPR 데이터시트(HTML) 7 Page - Texas Instruments |
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7 / 37 page ![]() www.ti.com RESET (Pin 35) t1 . 10 ms t2 . 2 ms t3 . 2 ms SEN Active Power Supply (AVDD, DRVDD) RESET TIMING CHARACTERISTICS Production Data ADS5541 SBAS307C – MAY 2004 – REVISED FEBRUARY 2007 Figure 2. Reset Timing Diagram Typical values given at TA = +25°C, min and max specified over the full temperature range of –40°C to +85°C, AVDD = DRVDD = 3.3V, and 3VPP differential clock, unless otherwise noted. ADS5541 PARAMETER DESCRIPTION MIN TYP MAX UNIT Switching Specification t1 Power-on delay Delay from power-on of AVDD and DRVDD to RESET pulse 10 ms t2 Reset pulse width Pulse width of active RESET signal 2 µs t3 Register write delay Delay from RESET disable to SEN active 2 µs Power-up time Delay from power-up of AVDD and DRVDD to output stable 40 ms 7 Submit Documentation Feedback |
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