전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

ADE3700SX 데이터시트(PDF) 18 Page - STMicroelectronics

부품명 ADE3700SX
상세설명  Analog LCD Display Engine for XGA and SXGA Resolutions
PDF  89 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ADE3700SX 데이터시트(HTML) 18 Page - STMicroelectronics

Back Button ADE3700SX Datasheet HTML 14Page - STMicroelectronics ADE3700SX Datasheet HTML 15Page - STMicroelectronics ADE3700SX Datasheet HTML 16Page - STMicroelectronics ADE3700SX Datasheet HTML 17Page - STMicroelectronics ADE3700SX Datasheet HTML 18Page - STMicroelectronics ADE3700SX Datasheet HTML 19Page - STMicroelectronics ADE3700SX Datasheet HTML 20Page - STMicroelectronics ADE3700SX Datasheet HTML 21Page - STMicroelectronics ADE3700SX Datasheet HTML 22Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 89 page
background image
Line Lock PLL
ADE3700
18/89
2.4
Line Lock PLL
The Line Lock PLL recovers a sample clock from an incoming hsync source. The response
characteristics of the line lock PLL can be adjusted for optimum response time and jitter filtering.
The phase of the sample clock can be digitally adjusted in steps of 289 ps (with a 27-MHz crystal).
The I2C interface of the line lock PLL is in the LLK_CTRL clock domain which must be active for
programming.
The PLL filter has three ranges with independent filter parameters. When the phase detector error
stays below a programmable threshold for a programmable number of input lines, the PLL filter
coefficients are changed. Any phase detector error above the programmed threshold will return the
filter to the appropriate level in one line. The operation is shown in Figure 3.
The digital loop filter is controlled by three parameters: MFACTOR, A and B. M_FACTOR is the
desired number of clocks per input line. The A and B parameters control the response of the 2nd
order digital filter. A and B are composed of a linear and exponential component designated by the
L and E suffix, respectively. The relationship of these numbers to the classic 2nd order damping and
natural frequency are as follows:
Damping = AL x 2(AE-12) x SQRT(5 x M_FACTOR / (BL x 2BE))
Natural Frequency = SQRT(M_FACTOR x 5 x BL x 2(BE-34))
ADC_OFFSET_B
0x0329
R/W
[7:0]
0x0
Offset Control, Blue Channel
ADC_GAIN_R
0x032A
R/W
[7:0]
0x0
Gain Control, Red Channel
ADC_GAIN_G
0x032B
R/W
[7:0]
0x0
Gain Control, Green Channel
ADC_GAIN_B
0x032C
R/W
[7:0]
0x0
Gain Control, Blue Channel
Figure 3: Line Lock PLL
Table 6: ADC Registers (Sheet 2 of 2)
Register
Addr.
Mode
Bits
Default
Description
Fast
Slow
Lock
Error > SLOW_TOL
Error <= SLOW_TOL for
more than LOCK_LINE_NB
Error > LOCK_TOL
more than SLOW_LINE_NB
of lines
Error <= LOCK_TOL for
of lines



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com