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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8595 데이터시트(PDF) 12 Page - Wolfson Microelectronics plc |
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WM8595 데이터시트(HTML) 12 Page - Wolfson Microelectronics plc |
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12 / 82 page  WM8595 Production Data w PD, Rev 4.2, January 2011 12 DIGITAL AUDIO INTERFACE TIMING – SLAVE MODE Figure 3 Slave Mode Digital Audio Data Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25˚C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 80 ns BCLK pulse width high tBCH 30 ns BCLK pulse width low tBCL 30 ns LRCLK set-up time to BCLK rising edge tLRSU 22 ns LRCLK hold time from BCLK rising edge tLRH 25 ns DACDAT (input) hold time from LRCLK rising edge tDH 25 ns DACDAT (input) set-up time to BCLK rising edge tDS 25 ns ADCDAT (output) propagation delay from BCLK falling edge tDD 4 16 ns Table 3 Slave Mode Audio Interface Timing |
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