WM8993 datasheet(112/229 Pages) WOLFSON

112 / 229 page

WM8993

Production Data

PD, November 2010, Rev 4.0

112

BCLK FREQUENCY

The BCLK frequency is controlled relative to CLK_SYS by the BCLK_DIV divider. Internal clock

divide and phase control mechanisms ensure that the BCLK and LRCLK edges will occur in a

predictable and repeatable position relative to each other and relative to the data for a given

combination of DAC/ADC sample rate and BCLK_DIV settings.

BCLK_DIV is defined in the “Digital Audio Interface Control” section. See also “Clocking and Sample

Rates” section for more information.

AUDIO DATA FORMATS (NORMAL MODE)

The audio data modes supported by the WM8993 are described below. Note that the polarity of the

BCLK and LRCLK signals can be inverted if required; the following descriptions all assume the

default, non-inverted polarity of these signals.

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 44 Right Justified Audio Interface (assuming n-bit word length)

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 45 Left Justified Audio Interface (assuming n-bit word length)

In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

WM8993 데이터시트(PDF) 112 Page - Wolfson Microelectronics plc