 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
WM8993 데이터시트(PDF) 29 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8993 데이터시트(HTML) 29 Page - Wolfson Microelectronics plc |
|
|
29 / 229 page  Production Data WM8993 w PD, November 2010, Rev 4.0 29 AUDIO INTERFACE TIMING MASTER MODE Figure 3 Audio Interface Timing - Master Mode Note that BCLK and LRCLK outputs can be inverted if required; Figure 3 shows the default, non- inverted polarity of these signals. Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode LRCLK propagation delay from BCLK falling edge tDL 20 ns ADCDAT propagation delay from BCLK falling edge tDDA 20 ns DACDAT setup time to BCLK rising edge tDST 20 ns DACDAT hold time from BCLK rising edge tDHT 10 ns Note that the descriptions above assume non-inverted polarity of BCLK and LRCLK. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
