| 전자부품 데이터시트 검색엔진 |
|
WM8993 데이터시트(PDF) 158 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8993 데이터시트(HTML) 158 Page - Wolfson Microelectronics plc |
|
158 / 229 page ![]() WM8993 Production Data w PD, November 2010, Rev 4.0 158 POWER ON RESET The WM8993 includes Power-On Reset (POR) circuits, which are used to reset the digital logic into a default state after power up. The POR circuits derive their output from AVDD1, AVDD2 and DCVDD. The internal POR ¯¯¯ signal is asserted low when AVDD1, AVDD2 and DCVDD are all below minimum thresholds. The specific behaviour of the circuit will vary, depending on relative timing of the supply voltages. Typical scenarios are illustrated in Figure 69 and Figure 70. Figure 69 Power On Reset timing – AVDD1/2 enabled first Figure 70 Power On Reset timing - DCVDD enabled first The POR ¯¯¯ signal is undefined until AVDD1 or AVDD2 has exceeded the minimum threshold, Vpora_on Once this threshold has been exceeded, POR ¯¯¯ is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Once AVDD1, AVDD2 and DCVDD have all |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |