WM8993 datasheet(173/229 Pages) WOLFSON

173 / 229 page

Production Data

WM8993

PD, November 2010, Rev 4.0

173

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

1011 = CLK_SYS / 22

1100 = CLK_SYS / 24

1101 = CLK_SYS / 32

1110 = CLK_SYS / 44

1111 = CLK_SYS / 48

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

Clocking 2

MCLK_SRC

MCLK Source Select

0 = MCLK pin

1 = GPIO1 pin

SYSCLK_SRC

CLK_SYS Source Select

0 = MCLK

1 = FLL output

MCLK_DIV

MCLK Divider

0 = MCLK

1 = MCLK / 2

MCLK_INV

MCLK Invert

0 = MCLK not inverted

1 = MCLK inverted

7:5

ADC_DIV [2:0]

000

ADC Sample Rate Divider

000 = CLK_SYS / 1

001 = CLK_SYS / 1.5

010 = CLK_SYS / 2

011 = CLK_SYS / 3

100 = CLK_SYS / 4

101 = CLK_SYS / 5.5

110 = CLK_SYS / 6

111= Reserved

Note - this field is ignored and invalid in Automatic

Clocking Configuration mode.

4:2

DAC_DIV [2:0]

000

DAC Sample Rate Divider

000 = CLK_SYS / 1

001 = CLK_SYS / 1.5

010 = CLK_SYS / 2

011 = CLK_SYS / 3

100 = CLK_SYS / 4

101 = CLK_SYS / 5.5

110 = CLK_SYS / 6

111= Reserved

Note - this field is ignored and invalid in Automatic

Clocking Configuration mode.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

ADCLRC

Generation

AIF_MSTR1

Audio Interface 1 Master Mode Select

0 = Slave mode

1 = Master mode

WM8993 데이터시트(PDF) 173 Page - Wolfson Microelectronics plc

WM8993 데이터시트(HTML) 173 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL