PC87393F datasheet(54/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.13.3

Serial Port 2 Configuration Register

This register is reset by hardware to 02h.

Location:

Index F0h

Type:

R/W

Bit

76543210

Name

Bank

Select

Enable

Reserved

Busy

Indicator

Power

Mode

Control

TRI-STATE

Control

Reset

00000010

Bit

Description

Bank Select Enable. Enables bank switching for Serial Port 2.

0: All attempts to access the extended registers in Serial Port 2 are ignored (default).

1: Enables bank switching for Serial Port 2.

6-3

Reserved

Busy Indicator. This read only bit can be used by power management software to decide when to power-down

the Serial Port 2 logical device.

0: No transfer in progress (default).

1: Transfer in progress.

Power Mode Control. When the logical device is active in:

0: Low power mode

Serial Port 2 clock disabled. The output signals are set to their default states. The RI input signal can be

programmed to generate an interrupt. Registers are maintained (unlike Active bit in index 30 that also

prevents access to Serial Port 2 registers).

1: Normal power mode

Serial Port 2 clock enabled. Serial Port 2 is functional when the logical device is active (default).

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

One exception is the IRTX pin, which is driven to 0 when Serial Port 2 is inactive and is not affected by this bit.

0: Disabled (default)

1: Enabled

PC87393F 데이터시트(PDF) 54 Page - National Semiconductor (TI)

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