PC87393F datasheet(88/148 Pages) NSC

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5.0 Game Port (GMP) (Continued)

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5.3.2

Game Port Control Register (GMPCTL)

This register affects the functionality of the Game Port only when operated in Enhanced mode (bit 0 of this register is set

to 1). Bits 1,2 and 4-7 affect Game Port functionality, as described in the table below.

Location:

Offset 00h

Type:

R/W

Bit

76543210

Name

Device B

Button 1

Debounce

Enable

Device B

Button 0

Debounce

Enable

Device A

Button 1

Debounce

Enable

Device A

Button 0

Debounce

Enable

Reserved

Device B

Pre-Scale

Enable

Device A

Pre-Scale

Enable

GMP

Enhanced

Mode

Enable

Reset

00000000

Required

Bit

Description

Device B Button 1 Debounce Enable. When set to 1, enables a 16 ms input debouncer on Device B Button 1

status input.

0: Disabled (default)

1: Enabled

Device B Button 0 Debounce Enable. Same as bit 7, but for Device B Button 0.

0: Disabled (default)

1: Enabled

Device A Button 1 Debounce Enable. Same as bit 7, but for Device A Button 1.

0: Disabled (default)

1: Enabled

Device A Button 0 Debounce Enable. Same as bit 7, but for Device A Button 0.

0: Disabled (default)

1: Enabled

Reserved

Device B Pre-Scale Enable. This bit determines the clock frequency used by Device B position counters.

0: 1 MHz (default)

1: 500 KHz

Device A Pre-Scale Enable. This bit determines the clock frequency used by Device A position counters.

0: 1 MHz (default)

1: 500 KHz

GMP Enhanced Mode Enable

0: Disabled (default)

1: Enabled

PC87393F 데이터시트(PDF) 88 Page - National Semiconductor (TI)

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