PC87393F datasheet(109/148 Pages) NSC

109 / 148 page

7.0 X-Bus Extension (Continued)

109

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Once a write cycle on the LPC falls within the range of any of the enabled decoded address ranges of the X-Bus functional

block, a write cycle begins. A write cycle (Figure 25) starts by outputting the address signals on address signals XA19-0,

and the data signals on data pins XD7-0, on the rising edge of the clock. One LPC clock cycle later, a chip select signals

XCS1 or 0 is asserted, based on the address accessed and the select signal mapping. Three clock cycles later, on the next

rising edge of the clock, the XWR signal is asserted (set to 0) indicating that this is a write cycle and enabling the device to

be written for 16 clock cycles plus the internally programmed wait state period. If XRDY use is enabled for this zone, XRDY

input value is then checked on the rising edge of the clock, and the transaction is extended until XRDY is detected to be high.

Five LPC clock cycles later, XWR is de-asserted (set to 1) and one clock cycle later, the transaction is completed by de-

asserting XCS1-0. Two clock cycle later, the address lines change their values to 0.

Figure 24. Read Access Cycle - Normal Address Mode

CLK

(Internal for

XD7-0

XA19-0

XCS1-0

XWR

Insert 12+”Programmed Wait States” of 33 MHz clocks here.

All non-clock signals remain the same during this inserted time.

XRD

XRDY

XD[7:0] (Data In)

(Data Read)

Reference)

PC87393F 데이터시트(PDF) 109 Page - National Semiconductor (TI)