PC87393F datasheet(119/148 Pages) NSC

119 / 148 page

7.0 X-Bus Extension (Continued)

119

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XA3-0

HA3-0

XD7-0

HA11-4

XA18-12

HA18-12

XSTB0

FXASTB

XRDY

HIOCHRDY

PIRQA-D

IRQ11, IRQ8, IRQ12, and IRQ1 respectively

GND

HMEMCS

If any of the functions multiplexed on XA18-12 (Game Port or Serial Port 2) are needed, use an external latch for these

signals.

Use the XRDY signal that is enabled upon reset. Either of the XIORD and XIOWR signals may be used. Set proper sys-

tem configuration before accessing a PC87570 or any I/O device with separate read and write signals for I/O and mem-

ory transactions.

2. Bear in mind the following system design hints for asynchronous X-Bus use:

The chip select signal should be used as a qualiﬁer with the address when partial address decoding is in use for mul-

tiple device access control.

In read cycles, the system may drive the data until the read signal XRD is de-asserted to guarantee the proper

PC8739x sampling.

In write cycles, use either the falling or rising edge of the write control signal (XWR) to latch the data in the device.

3. Address multiplexing on XDT7-0 and the XSTB2-0 is designed for glueless interface with off-chip latch components. See

the example using 74HCT373 latches in Figure 29.

Figure 29. Latched Mode X-Bus Transactions External Logic

(74HCT373)

D7-0

A27-20

A19-12

A3-0

XA3-0

XDT7-0

A11-4

Latch

(74HCT373)

Latch

(74HCT373)

Latch

XSTB0

XSTB1

XSTB2

PC8739

PC87393F 데이터시트(PDF) 119 Page - National Semiconductor (TI)

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