GX1 datasheet(39/247 Pages) NSC

39 / 247 page

Revision 1.0

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Signal Definitions (Continued)

2.2.5

Power, Ground, and No Connect Signals

Signal Name

BGA

Pin No.

SPGA

Pin No.

Type

Description

VSS

Refer to

Table 2-3

(Total of

71)

Refer to

Table 2-5

(Total of

50)

GND

Ground Connection

VCC2

Refer to

Table 2-3

(Total of

32)

Refer to

Table 2-5

(Total of

32)

PWR

1.6V, 1.8V, or 2.0V (nominal) Core Power Connection

VCC3

Refer to

Table 2-3

(Total of

32)

Refer to

Table 2-5

(Total of

18)

PWR

3.3V (nominal) I/O Power Connection

AC5

Q5, X2,

Z2,

AM36

No Connection

A line designated as NC must be left disconnected.

2.2.6

Internal Test and Measurement Signals

Signal Name

BGA

Pin No.

SPGA

Pin No.

Type

Description

FLT#

AC2

AJ3

Float

Float forces the GX1 processor to float all outputs in the high-

impedance state and to enter a power-down state.

RW_CLK

AE6

AL11

Raw Clock

This output is the GX1 processor clock. This debug signal can

be used to verify clock operation.

TEST[3:0]

B22, A23,

B21, C21

D28, B32,

D26, A33

SDRAM Test Outputs

These outputs are used for internal debug only.

TCLK

(PU)

Test Clock

JTAG test clock.

This pin is internally connected to a weak (>20-kohm) pull-up

resistor.

TDI

(PU)

Test Data Input

JTAG serial test-data input.

This pin is internally connected to a weak (>20-kohm) pull-up

resistor.

TDO

Test Data Output

JTAG serial test-data output.

TMS

(PU)

Test Mode Select

JTAG test-mode select.

This pin is internally connected to a weak (>20-kohm) pull-up

resistor.

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