DP8420V datasheet(13/60 Pages) NSC

13 / 60 page

40 Port A Access Modes

The DP8420V21V22V DP84T22 have two general pur-

pose access modes Mode 0 RAS synchronous and Mode 1

RAS asynchronous One of these modes is selected at pro-

gramming through the B1 input A Port A access to DRAM is

initiated by two input signals ADS (ALE) and CS The ac-

cess is always terminated by one signal AREQ These input

signals should be synchronous to the input clock

41 ACCESS MODE 0

Mode 0 synchronous access is selected by negating the

input B1 during programming (B1e0) To initiate a Mode 0

access ALE is pulse high and CS is asserted If precharge

time was met a refresh of DRAM or a Port B access was

not in progress the RAS (RASs) would be asserted on the

first rising edge of clock If a refresh or a Port B access is in

progress or precharge time is required the controller will

wait until these events have taken place and assert RAS

(RASs) on the next positive edge of clock

Sometime after the first positive edge of clock after ALE and

CS have been asserted the input AREQ must be asserted

In single port applications once AREQ is asserted CS can

be negated On the other hand ALE can stay asserted sev-

eral periods of clock however ALE must be negated before

or during the period of CLK in which AREQ is negated

The controller samples AREQ on the every rising edge of

clock after DTACK is asserted The access will end when

AREQ is sampled negated

TLF11109 – 9

FIGURE 8a Access Mode 0

DP8420V 데이터시트(PDF) 13 Page - National Semiconductor (TI)