DP8420V datasheet(18/60 Pages) NSC

18 / 60 page

40 Port A Access Modes (Continued)

452 Address Pipelining

Address pipelining is the overlapping of accesses to differ-

ent banks of DRAM If the majority of successive accesses

are to a different bank the accesses can be overlapped

Because of this overlapping the cycle time of the DRAM

accesses are greatly reduced The DP8420V21V22V

DP84T22 can be programmed to allow a new row address

to be placed on the DRAM address bus after the column

address hold time has been met At this time a new access

can be initiated with ADS or ALE depending on the access

mode while AREQ is used to sustain the current access

The DP8422V and DP84T22 support address pipelining for

Port A only This mode cannot be used with page static

column or nibble modes of operations because the DRAM

column address is switched back to the row address after

CAS is asserted This mode is programmed through ad-

dress bit R8 (see

Figures 11a and 11b ) In this mode the

output WE always functions as RFRQ

During address pipelining in Mode 0 shown in

Figure 11c

ALE cannot be pulsed high to start another access until

AREQ has been asserted for the previous access for at

least one period of CLK DTACK if programmed will be

negated once AREQ is negated WAIT if programmed to

insert wait states will be asserted once ALE and CS are

asserted

In Mode 1 shown in

Figure 11d ADS can be negated once

AREQ is asserted After meeting the minimum negated

pulse width for ADS ADS can again be asserted to start a

new access DTACK if programmed will be negated once

AREQ is negated WAIT if programmed will be asserted

once ADS is asserted

In either mode with either type of wait programmed the

DP8420V21V22V DP84T22 will still delay the access for

precharge if sequential accesses are to the same bank or if

a refresh takes place

TLF11109 – 15

FIGURE 11a Non-Address Pipelined Mode

TLF11109 – 16

FIGURE 11b Address Pipelined Mode

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