DP8422V datasheet(33/60 Pages) NSC

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70 RAS and CAS Configuration Modes (Continued)

72 MEMORY INTERLEAVING

Memory interleaving allows the cycle time of DRAMs to be

reduced by having sequential accesses to different memory

banks Since the DP8420V21V22V DP84T22 have sepa-

rate precharge counters per bank sequential accesses will

not be delayed if the accessed banks use different RAS

outputs To ensure different RAS outputs will be used a

mode is selected where either one or two RAS outputs will

be asserted during an access The bank select or selects

B0 and B1 are then tied to the least significant address bits

causing a different group of RASs to assert during each

sequential access as shown in

Figure 27 In this figure there

should be at least one clock period of all RAS’s negated

between different RAS’s being asserted to avoid the condi-

tion of a CAS before RAS refresh cycle

73 ADDRESS PIPELINING

Address pipelining allows several access RASstobeas-

serted at once Because RASs can overlap each bank re-

quires either a mode where one RAS and one CAS are used

per bank as shown in

Figure 28a or where two RASs and

two CASs are used per bank as shown in

Figure 28b Byte

writing can be accomplished in a 16-bit word system if two

RASs and two CASs are used per bank In other systems

WEs (or external gating on the CAS outputs) must be used

to perform byte writing If WEs are used separate data in

and data out buffers must be used If the array is not layed

out this way a CAS to a bank can be low before RAS which

will cause a refresh of the DRAM not an access To take

full advantage of address pipelining memory interleaving is

used To memory interleave the least significant address

bits should be tied to the bank select inputs to ensure that

all ‘‘back to back’’ sequential accesses are not delayed

since different memory banks are accessed

TLF11109 – 44

FIGURE 27 Memory Interleaving (C6 C5 C4 e 1 1 0 during Programming)

DP8422V 데이터시트(PDF) 33 Page - National Semiconductor (TI)