| 전자부품 데이터시트 검색엔진 |
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DP84902MS 데이터시트(PDF) 4 Page - National Semiconductor (TI) |
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DP84902MS 데이터시트(HTML) 4 Page - National Semiconductor (TI) |
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4 / 16 page ![]() DC and AC Device Specifications Absolute Maximum Ratings (Note) Note Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be oper- ated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ tables are not guaranteed at these ratings The ‘‘op- erating conditions’’ table will define the conditions for actual device operation Supply Voltage 7V TTL Input Maximum Voltage 7V Maximum Output Voltage 7V ESD Susceptibility (Note 1) 2000V Note 1 Human Body model used (100 pF through 15 kX) General Operating Conditions are guaranteed over supply voltage and operating ambient temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units Test (Note 1) VDD ECLVCC Supply Voltage 45 5 55 V NA TA Operation Ambient Temperature 0 70 C NA TS Storage Temperature b 65 150 C NA CLOAD Capacitive Load on any Output ECL Output 10 pF NA TTL Output 15 IOH High Logic Level Output Current b 8 mA (Note A) (CMOS Logic Outputs Only) IOL Low Logic Level Output Current EARLY LATE 6 mA (Note A) (CMOS Logic Outputs Only) All Others 8 (Note A) VIH High Logic Level Input Voltage 2 V (Note A) VIL Low Logic Level Input Voltage 08 V (Note A) fNRZ NRZ Transfer Rate Operating Frequency 5 50 Mbs (Note A) fSCLK SYNCCLK Operating Frequency 75 75 MHz (Note A) tPW(RESET) RESET Pulse Width (negative) 5 SYNCCLK (Note A) (See Figure 3 ) PERIODS tPW(RG WG) RG or WG Wait Time after Power Down or Reset SYNCCLK with Respect to Positive Edge of CRLS Pin 10 PERIODS (Note B) (See Figure 3 ) Note 1 Typical values are specified at 25 C and 5V supply Note A This parameter is guaranteed by outgoing testing Note B The limit values have been determined by characterization data No outgoing tests are performed TLF11963 – 3 Note Power down mode selected in control register (see Table I) FIGURE 3 Reset Pin and Power Down Timing Diagram 4 |
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